Sunday, 26 January 2014
Saturday, 5 October 2013
M.Tech 2013 15 batch assignment questions
VLSI TECHNOLOGY AND DESIGN
Assignment
Questions
______________________________________________________________________________
1) a) Explain the process of fabrication for CMOS
technology with neat diagrams?
b)
Compare BiCMOS technology with other Technologies?
2)
a) Explain the fabrication steps for nMos Technology.
b) Explain the pseudo-NMOS logic during the
low to high transition?
3) a) explain the scalable design rules with
equation?
b) Draw the transfer characteristics of CMOS
inverter and explain its operation?
4)
a) Discuss the significance of threshold voltage with input to
fabrication parameters?
b)
What is Latch up? How to prevent Latch up?
5) a) Explain how gm & gds are depend on fabrication
parameters?
b)
Derive the relation between Zpu and Zpd of BiCMOS inverter.?
6) a) What is Resistive interconnect delay? Why
it is present in logic circuits?
b) Draw the layout for NAND gate?
7)
a) Give some examples for low power gates?
b) What is switch logic? How it differ from
other logic design?
MICROCONTROLLERS
FOR EMBEDDED SYSTEM DESIGN
Assignment Questions
______________________________________________________________________________
UNIT-I
1) Explain ARM Design
Philosophy and also explain Instruction Pipeline.
2) Explain Interrupt and
Interrupt Vector Table, Program Status Register of ARM. Also list various
registers of ARM.
3) List out the various ARM
processor families with respect to the Architecture Revision.
UNIT-II
1) Explain ARM Programming
model and also list out various instructions of Instruction set i.e., a)
Addressing modes
b) Branch, Load Instructions
c) PSR Instructions
d) Conditional Instructions
e) Store Instructions
f) Data Processing Instructions
UNIT-III
1) Explain Thumb Instruction
set:
a) Data Processing
Instructions
b) Single-Register and Multi
Register Instructions
c) Load-Store Instructions
d) Register Usage
Instructions
e) Software Interrupt
Instructions
DIGITAL SYSTEM DESIGN
Assignment
Questions
________________________________________________________________________
1)
Implement a BCD- to excess three code
converter by ROM. Calculate the cross point density of the implementation.
2)
For a PLA with the following function
z1(x1x2x3)
= x1: z2(x1x2x3) = x1x2’+x1’x2: z3(x1x2x3) = x2’x3+x2x3’
Show the schematic diagram, show its SSR
notation and draw NMOS nor-nor implementation.
3)
Explain the Boolean difference method
with an example.
4)
A two level AND-OR circuit has four
AND gates feeding one OR gate.
The four AND gates realize the product
terms x1x3’x4, x2x4, x1’x3’x4’ and x1x2x3 respectively. Derive the a and b -
tests for detecting multiple stuck at faults.
5)
Find the minimized PLA of the
following output Boolean function by a PLA minimizer.
f1 = (2,4,5,6,7,10,14,15): f2 =
(4,5,7,11,15)
6)
Draw the portion of an ASM chart that
specify a conditional operation to increment register (r) during state t1 and
transfer to state t2 if control inputs z and y are equal to 1 and 0
respectively.
7)
Design an ASM chart for a serial adder
with accumulator and show the control block diagram.
8)
Explain the implementation of
Binary multiplier
CPLD AND FPGA
ARCHITECURES AND APPLICATIONS
Assignment Questions
______________________________________________________________________________
1) Write a short notes on
a) PAL
b) PLA
c) PEEL
d) FPGA(Features, Block
Diagram, Advantages)
2) i) Give the differences
between CPLD and FPGA.
ii) Write short notes on GAL (Generic
Array Logic).
3) Explain complex PLDs in
short.
4) Explain features of XC9500
CPLD family with architecture, block schematic.
5) Implement parallel adder
with Accumulation with CPLD
6) Explain different FPGA
programming types:
a) SRAM Programming Volatile
b) EPROM FPGA non-volatile
c) Fuse based FPGA
7) Explain in detail about PLB
architectures of FPGA.
8) Write short notes on
Programmable I/O blocks, Programmable interconnects in FPGA. Also list applications
of FPGA.
Assignment Questions
______________________________________________________________________________
UNIT-I
1) Define
Combinational and Sequential logic circuits. Explain various parameters of
Pseudo NMOS logic Inverter i.e., Inverter threshold voltage, Output high
voltage, Output Low voltage, Gain at gate threshold voltage, Transient
response, Rise time, Fall time.
2) Explain
Pseudo NMOS logic gates with Transistor equivalency circuits. Also explain CMOS
Inverter logic circuits.
UNIT-II
1)
Design CMOS Full adder, CMOS Transmission
gates with necessary equations and tables.
2)
Design Complex logic circuits realizing
Boolean expressions using NMOS and CMOS gates.
3)
Explain MOS logic circuits with NMOS loads
and also write a short note on AOI and OAI gates.
UNIT-III
1)
Write a short note on
a) SR Latch
b) Clocked Latch
c) Flipflops using
Sequential MOS logic circuits.
2) Explain
behavior of Bistable elements, Edge Triggered flipflops and CMOS D-Latch in
Sequential
MOS Logic circuits.
CMOS ANALOG
INTEGRATED CIRCUIT DESIGN
Assignment Questions
______________________________________________________________________________
UNIT-I
1) Explain
Integrated circuit Layout and MOS Transistor.
2) Explain
CMOS device modeling with Simple MOS Large-Signal Model. List out the model
parameters of CMOS Device modeling.
UNIT-II
1)
Write a short notes on
a)
MOS switch, MOS Diode
b)
Current sinks and sources
c)
Cascode current mirror and Wilson current
mirror.
2)
Explain Analog current mirrors with Beta
helper.
UNIT-III
1)
a) Define Amplifier.
b) Write a short
note on Differential Amplifier, Current amplifier, Cascode Amplifier,
Inverters.
2) Explain with necessary equations and
diagrams, High gain CMOS Amplifier Architectures.
Thursday, 5 September 2013
Academic Calendar for M.Tech I, II, III, IV Semester's [For 2013 Admitted Batch]
Academic
Calendar for M.Tech I, II, III, IV Semester's
[For
2013 Admitted Batch]
M.Tech I semester (2013-2014)
|
Event
|
From
|
To
|
No.of Weeks/Days
|
|
Report & Orientation Programme
|
02.09.2013
|
-
|
-
|
|
I Spell of Instructions
|
02.09.2013
|
11.10.2013
|
6
Weeks
|
|
Dusserah Holidays
|
12.10.2013
|
20.10.2013
|
9
Days
|
|
I mid examinations
|
04.11.2013
|
09.11.2013
|
1
week
|
|
II Spell of Instructions
|
11.11.2013
|
04.01.2014
|
8
Weeks
|
|
II mid examinations
|
06.01.2014
|
10.01.2014
|
1
Week
|
|
Pongal Holidays
|
11.01.2014
|
18.01.2014
|
1
Week
|
|
Preparations & Practical
examinations
|
20.01.2014
|
01.02.2014
|
2
Weeks
|
|
End semester examinations
|
03.02.2014
|
15.02.2014
|
2
Weeks
|
|
Commencement of class work for II
semester
|
17.02.2014
|
-
|
-
|
M.Tech II semester (2013-2014)
|
Event
|
From
|
To
|
No.of Weeks/Days
|
|
I Spell of Instructions
|
17.02.2014
|
12.04.2014
|
8
Weeks
|
|
I mid examinations
|
14.04.2014
|
19.04.2014
|
1
week
|
|
II Spell of Instructions
|
21.04.2014
|
17.05.2014
|
4
Weeks
|
|
Summer Vacation
|
18.05.2014
|
15.06.2014
|
4
Weeks
|
|
II Spell of Instructions
Continuation
|
16.06.2014
|
12.07.2014
|
4
Weeks
|
|
II mid examinations
|
14.07.2014
|
19.07.2014
|
1
Week
|
|
Preparations & Practical
examinations
|
21.07.2014
|
02.08.2014
|
2
Weeks
|
|
End semester examinations
|
04.08.2014
|
16.08.2014
|
2
Weeks
|
M.Tech III & IV Semester's (2014-2015)
|
Event
|
From
|
To
|
No. of Weeks/Days
|
|
III Semester
|
18.08.2014
|
17.01.2015
|
22
Weeks
|
|
Seminar Dates
|
19.01.2015
|
20.01.2015
|
2
Days
|
|
IV Semester
|
21.01.2015
|
06.06.2015
|
22
Weeks
|
|
Thesis Submission Duration
|
08.06.2015
|
21.11.2015
|
24
Weeks
|
Tuesday, 30 April 2013
Monday, 29 April 2013
IMPORTANT LINKS TO STUDENTS
http://www.youtube.com/iit - IIT Lectures visit for subject related doubts.
http://nptel.iitm.ac.in/ - NATIONAL PROGRAMME ON TECHNOLOGY ENHANCED LEARNING (NPTEL )
Subscribe to:
Posts (Atom)